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01/99
IFPA300, IFPA301
Monolithic JFET Preamplifier
Description & Features
The IFPA300 series is an inverting transimpedance amplifier featuring extremely low noise and a wide gain-bandwidth suitable as a charge-sensitive preamplifier for a broad range of applications. The monolithic IFPA300 series contain 8 n-channel epitaxial-channel diffused-gate JFETs to achieve optimally low 1/f noise performance over a wide temperature range (120K-300K).
DC open loop gain GBW eN @ 10 Hz 85 dB 200 MHz 3.0 nV/Hz
Absolute maximum ratings at TA = 25C
All pins (except Input) referenced to Bias 3 Input to Bias 3 Power Dissipation Derating Factor Operating Temperature 85 dB OV 225 mW 1.8 mW/C 150C
At this time, there are two units in this family.
The 300/301 Series gives more flexibility with respect to output transistor drain. The 310/311 Series ties the output transistor drain to the VDD line.
Simplified Schematic Circuit
General Specifications
Power Dissipation at VDD = 12 V Input Leakage Current (T = 300 K) Input-Referred Noise Voltage (f = 10 kHz) Input-Referred Noise Voltage (f = 10 Hz) Output Range at VDD = 12 V Designed to drive 50 load. <100 mW 10 pA 0.6 nV/Hz 3.0 nV/Hz 4.0 V (5.0 V Max)
J4 J7 J3
VDD
Substrate
Charge Sensitive Preamplifier Specifications
The IFPA300 Series is actually tailored to detector capacitance in the 100 1000 pF range.
Input Open-Loop Capacitance Rise Time (CD = 500 pF, Cf = 33 pF) 60 pF 20 ns
Bias 1
J2 J6
J8
Open Drain Output Open Source Output
Bias 2 Input
J1 J5 VSS
Equivalent Noise Charge
(Measured with semigaussian shaping, peaking time = tp)
4200 e- rms at CD @ 500 pF, tp = 0.2 m 3200 e- rms at CD @ 500 pF, tp = 1.0 m 4200 e- rms at CD @ 500 pF, tp = 4.0 m
Bias 3
Packages & Test Circuit Overside
1000 N. Shiloh Road, Garland, TX 75042 (972) 487-1287 FAX (972) 276-3375
www.interfet.com
01/99
xi
IFPA300, IFPA301
Monolithic JFET Preamplifier
Input FET J1 selected to the following elecrical parameters.
Parameter BVGSS IGSS IDSS VGS(OFF) GM VGSF Conditions Vds = 0, Ig = 1 A Vds = 0, Vgs = - 10 V Vds = 0, Vgs = 10 V Vds = 0, Id = 1 A Vgs = 0, Vds = 10 V Id = 1 A 40 1 50 0.35 0.65 Min - 25 2 500 2 Max Units Volts nA mA Volts mM Volts
Bias 2 Bias 1
J2 J6 J8 VDD = +12 V
DUT
J4 VDD J7 J3
120K
Substrate Open Drain Output Open Source Output
Test Point #
Test Circuit Reference
Parameter VDCout Vin VACout VACout Conditions Vdd = 12 V, - VS = - 6 V Test pt #1 Vdd = 12 V, - VS = - 6 V Test pt #2 Vdd = 12 V, - VS = - 6 V t = O sec Vdd = 12 V, - VS = - 6 V t = 100 sec Min 6 - 0.6 50 20 Max 10 - 1.6 Units V
Input 20K
J1
J5 VSS
Bias 3
V mV mV
10pF AC Input Test Point #2 2M 1M 10pF
10K
- Vsupply = - 6 V
0.165 (4.19) 0.185 (4.70) 0.335 (8.51) 0.370 (9.40) 0.305 (7.75) 0.335 (8.51)
0.010 (0.25) 0.040 (1.02) 8 Leads - Dia. 0.016 (0.41) 0.021 (0.53)
0.029 (0.74) 0.045 (1.14) 0.200 (5.08) Basic 5 4 45 3 2 1 6 7
8765 Top 1234
0.244 (6.20) 0.158 (4.01) 0.228 (5.79) 0.150 (3.81) 0.028 (0.71) 0.024 (0.61)
0.050 (1.27)
8
0.022 (0.56) 0.018 (0.046
0.018 (0.46 0.014 (0.36) 0.049 (1.24) 0.059 (1.50)
0.015 (0.37) Min. 0.069 (1.75) 0.053 (1.35)
45
0.010 (0.25) 0.040 (1.02) 0.500 (12.70)
Standoff 0.110 (2.79) 0.160 (4.06)
0.028 (0.71) Bottom View 0.034 (0.86)
0.197 (5.00) 0.188 (4.78)
0.009 (0.23) 0.007 (0.18)
IFPA300 uses TO-99 Package
Dimensions in Inches (mm)
IFPA301 uses SOIC-8 Package
Dimensions in Inches (mm)
Pin Configuration
1 Bias 3, 2 VSS, 3 Bias 1, 4 VDD /Substrate 5 Open Drain Output, 6 Open Source Output, 7 Bias 2, 8 Input
Pin Configuration
1 Bias 2, 2 Input, 3 Bias 3, 4 VSS, 5 Bias 1, 6 VDD/Substrate 7 Open Drain Output, 8 Open Source Output
www.interfet.com
1000 N. Shiloh Road, Garland, TX 75042 (972) 487-1287 FAX (972) 276-3375

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